Parallel-plate structure fabrication method and parallel-plate structure arrangement

ABSTRACT

A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

FIELD OF THE INVENTION

The present invention relates to a parallel-plate structure fabrication method. Especially the present invention relates to a parallel-plate structure fabrication method for ferroelectric and piezoelectric thin film structure and to fabrication method for integrated structures based on said structures and e.g. thick metal inductors.

The present invention also relates to parallel-plate structures, and especially to e.g. ferroelectric and piezoelectric thin film structures and integrated structures based on the said structures and e.g. thick metal inductors.

BACKGROUND OF THE INVENTION

Perovskite metal-oxides, such as Ba_(x)Sr_(1-x)TiO₃ (hereinafter called “BST”), show exceptional material properties including (i) switchable permanent polarization (ferroelectric phase), (ii) piezoelectricity (ferroelectric phase), (iii) field-dependent (tunable) polarization (paraelectric phase), (iv) low losses at high frequencies (paraelectric phase). Tunability and low losses, typically obtained in the paraelectric phase, make these materials of special interest for high-frequency applications. An example of a basic device realizable using these materials is a tunable capacitor (varactor).

For optimal tunability, parallel-plate device geometry is highly desirable: here the perovskite metal-oxide is sandwiched between two (top and bottom) metallic electrodes. Using planar device geometries based on metal electrodes deposited only on top of the perovskite metal-oxide, it is difficult to obtain sufficient tunability.

In the prior art parallel-plate capacitor fabrication process, the layers are deposited successively on a substrate, ie. the metallic bottom electrode is first deposited on the substrate, then the BST layer is deposited on the metallic bottom electrode and finally the metallic top electrode is deposited on the BST.

High processing temperatures are required for proper crystallization of perovskite oxides (e.g. for BST, T_(min)˜650° C.). The high temperature and the presence of oxygen make the parallel-plate device processing problematic. The metallic bottom electrode is heavily attacked during BST growth. Typical problems encountered in the bottom electrode are (i) electrode destruction via oxidation, (ii) grain growth resulting in poor BST quality. On the other hand, the electrode material should be well conducting to prevent the critical losses at high frequencies. Of typical metals, Cu, Ag, Al, and Au are well conducting but either get easily oxidized and/or are unstable substrates for BST growth due to their low melting point. A typical state-of-the-art choice for the bottom electrode is Pt, which, however, (i) is a significantly worse conductor than the metals above, (ii) will easily exhibit grain growth if thick layers are employed to reduce conductor losses. Furthermore, Pt is permeable with respect to oxygen, and reactive with respect to other metals—both effects complicating the fabrication of multilayered electrode structures. The refractory metals (Mo,W) are more stable against grain growth and they are intermediate conductors but get easily oxidized. Protective layers (e.g. diffusion barriers) can in principle be employed to protect the bottom electrode from oxidation, but it is difficult to obtain a well-protecting layer with minimal parasitic effects (e.g. non-tunable capacitance).

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to eliminate the disadvantages of the prior art parallel-plate structure fabrication methods and to provide an improved method for fabrication of parallel-plate structures.

It is further an object of the present invention to eliminate the disadvantages of the prior art parallel-plate structures and to provide an improved parallel-plate structure arrangement.

The present invention provides a solution to the disadvantages of the prior art with an improved fabrication method which is based on layer transfer fabrication techniques and utilizes an auxiliary substrate on which the BST or a corresponding middle layer is first deposited.

In the invented processing method BST or another suitable material is grown first and the top and bottom electrodes are essentially deposited second utilizing layer transfer. Characteristic features of the present invention are in detail presented in the enclosed claims.

Key advantages of the present invention are:

BST or corresponding middle layer growth can be done in optimal conditions to obtain high BST or corresponding middle layer quality. E.g. high growth temperatures and the highly oxidizing growth atmosphere can be used without the risk of electrode destruction.

a wide variety of metals, including e.g. Cu, can be used for electrodes as metal oxidation and/or high-temperature grain growth are no more an issue

all key layers (bottom metal electrode, middle layer, like BST, top metal electrode) can be patterned. In particular, contacts to bottom electrode can be easily made

by employing a structure where two capacitors are connected in series and are inversely biased, the even-order nonlinearities will be removed or strongly attenuated,

it is possible to implement integrated structures including tunable capacitors and additional integrated components such as (i) several inductors or further capacitors, (ii) resistors (e.g. for biasing), (iii) non-tunable capacitors,

the process can be integrated as part of IPD (Integrated Passive Device) fabrication process. Tunable, low-loss capacitors combined with high-Q inductors (thick Cu, low-loss glass substrate), integrated resistors, etc. allow the creation of attractive applications such as excellent phase noise VCO:s, tunable impedance matching networks or filters, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing, and additional objects, features and advantages of the present invention will be more clearly understood from the following detailed description of preferred embodiments of the present invention, taken in conjunction with accompanying drawings, in which:

FIGS. 1 a to 1 d present process schematics for ferroelectric or piezoelectric (e.g. BST) thin film capacitor fabrication via layer transfer method.

FIG. 2 presents a preferred embodiment of including layers acting to improve electrode material adhesion and/or to served as diffusion barriers

FIGS. 3 a and 3 b present preferred embodiments, where the processed layers, in particular the middle (e.g. BST) layer and the electrode layers, are patterned to create desired capacitor structures.

FIGS. 4 a and 4 b present a preferred embodiment where two ferroelectric capacitors are placed in series and a DC contact is created to the (bottom) electrode contacting the two capacitors.

FIGS. 5 a to 5 c present a side view and top view as well as coupling schema of a preferred embodiment where electrodeposition is employed to realize low-loss inductor structures via the thick top electrode layer, thereby allowing integrated, high-performance tunable LC-structures.

FIGS. 6 a to 6 c present a side view and top view as well as coupling schema of another preferred embodiment where the low-loss inductor structures and the ferroelectric capacitors are used to realize an integrated, tunable impedance matching circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 a to 1 d present process schematics for thin film capacitor fabrication via layer transfer method. The middle ferroelectric or piezoelectric (e.g. BST) layer 102 is sandwiched between two (top and bottom) metallic electrodes 101, 103 (see e.g. FIG. 1 d).

The method is in detail illustrated in the following with reference to the following process steps: (1-2) BST growth and bottom electrode deposition on the first substrate (FIG. 1 a), (3) layer transfer from the first substrate to the second substrate (FIG. 1 b), (4) first substrate removal (FIGS. 1 c), and (5) top electrode deposition and (FIG. 1 d).

In the invented processing method, as outlined in FIGS. 1, the metal-oxide layer 102 is grown first and the top and bottom electrodes 101, 103 are essentially deposited second utilizing layer transfer.

(1) BST is grown on a first (auxiliary) substrate 104 (e.g. Si). The substrate will be later removed and therefore is to be suitably selected for this purpose. For optimal BST growth, a suitable seed layer 105 may be grown on substrate. Seed layer is optional and can be e.g. pure SiO₂ or thin Pt on SiO₂. As both bottom and top metal electrodes are in essence deposited after BST growth, the BST growth conditions can be chosen for optimal BST growth: e.g. optimally high temperatures can be used without the deterioration of metallic electrode.

(2) Bottom electrode 103 deposition after BST growth, on top of BST. The electrode metal can be rather freely selected, in particular it can be e.g. Cu, Al, Ag or Au. Since metal deposition can be done at low temperatures (e.g. T<200° C.), and oxygen is highly bound to already grown BST, the deposited metal is not heavily attacked by oxygen or temperature. The bottom metal electrode 103 can be patterned. Next, a buffer layer 106 is grown (e.g. thick SiO₂) which is planarized. The role of the buffer layer is to allow wafer bonding to a second (bottom) substrate 100 (e.g. glass). Alternatively, the buffer layer can be e.g. a polymer film (e.g. BCB, polyimide) deposited e.g. using spin coating.

(3) BST layer 102 transfer to a second substrate 100. The prepared BST wafer is bonded with the second substrate (e.g. glass).

(4) The first substrate removal after wafer bonding. Possible methods include, for example, : (i) chemical wet-etching of Si (HF+HNO3+CH3COOH), (ii) chemical-mechanical thinning (grinding, polishing) followed by plasma etching (e.g ICP, DRIE,). Key aspect in removal of the first substrate is etch selectivity: (a) e.g. seed layer of thin Pt can act as the etch stop after first substrate is removed, (b) the second substrate and BST are to be selective to the first substrate removal or are to be protected. The seed layer 105, if applied, can be optionally also removed before top electrode deposition.

(5) Top electrode 101 deposition. Metal can be freely selected as for the bottom electrode. As a result, the capacitor C1 having bottom and top electrodes 103, 101 and a middle layer 102 has been fabricated.

Additional layers serving as adhesion layers and/or diffusion barriers 107, 108 can be employed (e.g. TiW) between the BST and the top and the bottom electrodes as shown in FIG. 2.).

Patterning of the layers to obtain desired capacitor structures. As shown as an example in FIG. 3 a, the top electrode layer 111, the seed layer 115 for BST growth, the BST layer 112, and the bottom electrode layer 113 embedded in a top planarization layer 110 are patterned to create a two-capacitors-in-series structure accessible via the top metal contacts. In particular, the BST layer can be patterned before wafer bonding to control strain when transferring the BST thin film from the first substrate to the second substrate—i.e. to avoid BST cracking.

The process sequence easily allows also processing to create an ohmic contact creation to the bottom electrode 123 from the top metal 121 as shown in FIG. 3 b presenting the top electrode including a contact 130 to the bottom electrode. The capacitor C2 is formed between the top and bottom layers wherein further the bottom electrode is connected to another area 131 on the top layer in order to get an external contact.

FIG. 4 a shows a schematic structure where a DC contact 140 is realized to the bottom electrode 113 (see FIG. 3 a). The bottom electrode connects the two ferroelectric (tunable) capacitors in C3, C4 series. By connecting a tuning DC voltage DCin (typically via a high impedance route as illustrated by the resistor R in FIG. 4 b) to the bottom electrode, the two capacitors will be inversely biased, that is, the bias voltage UDC will be parallel to AC signal in one of the capacitors C3 while being antiparallel in the other capacitor C4. The key advantages of the preferred embodiment shown in FIGS. 4 a and 4 b are: (i) the even order nonlinearities (e.g. even harmonics) will be removed or strongly attenuated due to inverse biasing, (ii) a DC-block is realized to prevent the DC-voltage reaching the AC-contacts ACin, ACout. If desired, several copies of the structure described by FIGS. 4 a and 4 b can be connected in series to gain additional advantages.

Thick metal deposition methods, electrodeposition growth in particular, can be applied to obtain thick top metal conductors. As shown in FIG. 5 a, the top electrode is on the contrary to FIG. 1 d essentially thicker than the bottom electrode and consists of two layers 152, 153, the first layer 152 being a thin layer and the second layer 153 being a galvanic grown thicker layer 153 (typical thickness ratio 1:10 between the layer thicknesses). As further shown in FIGS. 5 a to 5 c , the thick top metal layer is utilized to create a low-loss (high-Q) inductor, which is connected with the dual inversely biased tunable capacitor structure described in FIGS. 4 a and 4 b. The resulting integrated structure has four electrical connections (AC1, AC2, AC3, DC3) which can be used to access a tunable, high-Q LC-circuit (parallel or series configuration). Such a tunable, high-Q LC-circuit can be used e.g. to realize a high performance voltage controlled oscillator (VCO) where the high tank Q-value, due to low-loss inductor and low-loss capacitors, results in excellent phase noise performance. Another key feature is the small second order nonlinearity due to inversely biased capacitors-configuration, which critically reduces the up-mixing of 1/f-noise.

Another preferred embodiment based on integrated low-loss inductors and tunable, ferroelectric capacitors is shown in FIGS. 6 a to 6 c, in which a first capacitor structure (accessible via contacts AC1 and AC2, tuning voltage inserted via DC1), a low-loss inductor L, and a second capacitor structure (accessible via contacts AC3 and AC4, tuning voltage inserted via DC2) are connected. A tunable “pi-network”, typically used as impedance matching network, can be realized e.g. by connecting contacts AC1 and AC4 to ground, using AC2 and AC3 as AC signal input and output, respectively, and using DC1 and DC2 as biasing voltage inputs to tune the first and the second capacitor structures. Of particular importance is again the capacitor structure in which the two capacitors are inversely biased resulting in low even-order nonlinearities, critical e.g. for harmonic distortion generation in wireless applications.

It is obvious to the person skilled in the art that the integrated structure described in FIGS. 4 a to 6 c may also include additional integrated components such as (i) several inductors or further capacitors, (ii) resistors (e.g. for biasing), (iii) non-tunable capacitors, etc. It is also obvious that the described structures are schematic and may not reflect the true dimensions or the true shape of the fabricated structures.

It is also obvious to the person skilled in the art that different embodiments of the invention are not limited to the examples described above, but that they may be varied within the scope of the enclosed claims. The process sequence is illustrated using BST as an example, but the method is applicable to any perovskite metal-oxide, or similar material, such as ZnO, AlN, SiO₂, Si₃N₄, CN, etc., that requires processing conditions destructive for the electrodes. It is also obvious that the capacitors may serve not only as lumped elements but also as part of distributed structures such as transmission lines. It is further obvious to the person skilled in the art that the present invention may be applied to the parallel plate structures that exhibit acoustic resonances which are transduced via piezoelectric or electrostrictive middle layer. Such structures can thus be operated as a FBAR (Thin Film Bulk Acoustic Resonator) or as a TFBAR (Tunable Thin Film Bulk Acoustic Resonator). Further, the structure may contain additional layers acting as acoustic mirrors. 

1. A fabrication method for parallel-plate structures, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, characterized in that in the method the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.
 2. The method according to claim 1, characterized in that in the method: the middle layer is first grown on a first substrate, the bottom electrode is deposited after the middle layer growth, the layer stack is transferred to a second substrate, the first substrate is removed, and the top electrode is deposited on top of the middle layer.
 3. The method according to claim 1, characterized in that the processing conditions for optimal middle layer growth are destructive for opti-mal electrode materials.
 4. The method according to claim 1, characterized in that the middle layer is ceramic material, such as metal oxide, metal nitride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties or a com-bination of those.
 5. The method according to claim 1, characterized in that the middle layer is perovskite material such as Ba_(x)Sr_(1-x)TiO₃, or piezoelectric material such as ZnO, AlN.
 6. The method according to claim 1, characterised in that the middle layer is a stack of layers made of materials in claims 4 and
 5. 7. The method according to claim 1, characterised in that the bottom and the top electrodes are of electrically conductive material.
 8. The method according to claim 1, characterised in that the bottom and the top electrodes are metal, such as Cu, Al, Au, Ag, Pt.
 9. The method according to claim 1, characterised in that adhesion layers and/or diffusion barriers are applied between the bottom and top electrodes and the middle layer.
 10. The method according to claim 1, characterised in that in the bottom and/or top electrodes are/is patterned.
 11. The method according to claim 1, characterised in that a buffer layer is deposited and suitably processed (e.g. ground and polished) in order to allow wafer bonding to a second (bottom) substrate.
 12. The method according to claim 1, characterised in that the prepared first wafer, on which the middle layer and the bottom electrode reside, is bonded with the second substrate, and that after bonding, the first substrate is removed.
 13. The method according to claim 12, characterised in that in removal of the first substrate is implemented etch selectively: (a) etch stop after first substrate is removed, and (b) the second substrate and the middle layer are selective to the first substrate removal or are protected, or by chemical-mechanical thinning (grinding, polishing) followed by plasma etching (e.g ICP, DRIE).
 14. The method according to claim 1, characterised in that the middle layer compound is patterned before or after wafer bonding.
 15. The method according to claim 14, characterized in that the patterning is implemented for ohmic contact creation to the bottom metal electrode from the top metal electrode.
 16. The method according to claim 1, characterized in that the electrodeposition growth is applied to obtain thick top metal conductors.
 17. A parallel-plate structure arrangement obtainable by a fabrication method, wherein the structures have a middle layer grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, characterized in that in the method the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.
 18. The arrangement according to claim 17, characterized in that in the method: the middle layer is first grown on a first substrate, the bottom electrode is deposited after the middle layer growth, the layer stack is transferred to a second substrate, the first substrate is removed, and the top electrode is deposited on top of the middle layer.
 19. The arrangement according to claim 17, characterized in that the processing conditions for optimal middle layer growth are destructive for optimal electrode materials.
 20. The arrangement according to claim 17, characterized in that the middle layer is ceramic material, such as metal oxide, metal ni-tride, metal fluoride, featuring ferroelectric, paraelectric or piezoelectric properties or a combination of those.
 21. The arrangement according to claim 17, characterized in that the middle layer is perovskite material such as Ba_(x)Sr—I—XTiO₃, or piezoelectric material such as ZnO, AIN.
 22. The arrangement according to claim 17, characterized in that the middle layer is a stack of layers made of materials in claims 20 and
 21. 23. The arrangement according to claim 17, characterized in that the bottom and the top electrodes are of electrically conductive material.
 24. The arrangement according to claim 17, characterized in that the bottom and the top electrodes are metal, such as Cu, Al, Au, Ag, Pt.
 25. The arrangement according to claim 17, characterized in that adhesion layers and/or diffusion barriers are applied between the bottom and top electrodes and the middle layer.
 26. The arrangement according to claim 17, characterized in that in the bottom and/or top electrodes are/is patterned.
 27. The arrangement according to claim 17, characterized in that a buffer layer is deposited in order to allow wafer bonding to a second (bottom) substrate.
 28. The arrangement according to claim 17, characterized in that the prepared first wafer, on which the middle layer and the bottom electrode reside, is bonded with the second substrate, and that after bonding, the first substrate is removed.
 29. The arrangement according to claim 17, characterized in that in removal of the first substrate is implemented etch selectively: (a) etch stop after first substrate is removed, and (b) the second substrate and the middle layer are selective to the first substrate removal or are protected, or by chemical-mechanical thinning (grinding, polishing) followed by plasma etching (e.g ICP, DRIE).
 30. The arrangement according to claim 17, characterized in that the middle layer compound is patterned before or after wafer bonding.
 31. The arrangement according to claim 30, characterized in that the patterning is implemented for ohmic contact creation to the bottom metal electrode from the top metal electrode.
 32. The arrangement according to claim 17, characterized in that electrodeposition is applied to obtain thick top metal conductors.
 33. The arrangement according to claim 17, characterized in that the structure is a capacitor arrangement.
 34. The arrangement according to claim 17, characterized in that the second substrate is glass or similar insulating material featuring low RF-losses.
 35. The arrangement according to claim 17, characterized in that the arrangement forms an integrated structure, whereby the structure or structures are applied to small areas on a larger substrate area, and that the same wafers include additional integrated components such as (i) several inductors or further capacitors, (ii) resistors (e.g. for biasing), (iii) non-tunable capacitors.
 36. The arrangement according to claim 31, characterized in that the top electrode includes a contact to the bottom electrode, whereby a structure is formed between the top and bottom layers wherein further the bottom electrode is connected to another area on the top layer in order to get an external contact.
 37. The arrangement according to claim 17, characterized in a structure where a DC contact is realized to the bottom electrode, whereby the bottom electrode connects the two ferroelectric structures in series.
 38. The arrangement according to claim 37, characterized in that by connecting a tuning DC voltage to the bottom electrode, the two structures will be inversely biased.
 39. The arrangement according to claim 32, characterized in that the thick top metal layer is provided with a low-loss inductor, which is connected with the dual inversely biased structure.
 40. The arrangement according to claim 32, characterized in that the structure includes a first capacitor structure, a low-loss inductor, and a second capacitor structure.
 41. The arrangement according to claim 17, characterized in that the capacitor(s) is/are tunable.
 42. The arrangement according to claim 17, characterized in that an additional layer or additional layers serving as adhesion layer(s) and/or diffusion barrier(s) is/are employed (e.g. TiW) between the middle, top and/or the bottom electrodes.
 43. The method according to claim 1, characterized in that the processed structure or part of the structure exhibits acoustic wave resonances and is operated as a FBAR (Thin Film Bulk Acoustic Resonator) or as a TFBAR (Tunable Thin Film Bulk Acoustic Resonator).
 44. The arrangement according to claim 17, characterized in that the processed structure or part of the structure exhibits acoustic wave resonances and is operated as a FBAR (Thin Film Bulk Acoustic Resonator) or as a TFBAR (Tunable Thin Film Bulk Acoustic Resonator).
 45. The method according to claim 1, characterized in that the processed structure additional layer or layers are deposited acting as acoustic mirror(s).
 46. The arrangement according to claim 17, characterized in that the processed structure contains additional layer or layers acting as acoustic mirror(s). 